Dr. Ritu Pahwa
Associate Professor and Head of Department CSE(AI&ML)
Google Scholar page : https://scholar.google.com/citations?user=mDOT21Qb6mMC&hl=en
Dr. Ritu Pahwa is a proficient and diligent professional with a wealth of expertise in the field of Electronics and Communication Engineering with specialization in Artificial Intelligence and Machine Learning.
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Perpetual and Passionate Learner
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Amazing work ethics
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Incredible problem-solver
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Artistic
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Good Orator
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Virtuous Team-building skills
Education
Ph.D. (Electronics & Communication Engineering, USIC&T, GGSIPU, New Delhi)
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Ph.D. form Guru Gobind Singh Indraprastha University, (New Delhi) in Department of Electronics & Communication Engineering in regular mode on topic “Non-Invasive Electrocardiogram Extraction and Analysis using Wavelet and Machine Learning Techniques”. (Defended Viva on 13/09/2021)
Master of Engineering (Electronics & Communication Engineering)
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Academic year 2005-2007
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Vaish College of Engineering, Rohtak, (Maharishi Dayanand University)
Bachelor of Engineering (Electronics)
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Academic year 1993-1997
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K. K. Wagh Institute of Engineering Education & Research, Nasik, (Pune University).
Experience
Associate Professor and Head of Department CSE(AI&ML)
Dronacharya College of Engineering, Khentawas, Farrukhnagar, Gurgaon – Haryana
Associate Professor
IITM Janakpuri Delhi
Assistant Professor
Vaish College of Engineering, Rohtak, Haryana
Lecturar
Vaish College of Engineering, Rohtak, Haryana
Training
Himachal Futuristic Communication Ltd., Gurgaon
Trainer
Aptech Computer Centre, Rohtak
Project Undergone
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Lighting arrestor element fall counter & peak volt hold meter in 1996-97.
(Sponsored by Crompton Greaves Switch Gear Complex Ambad (MIDC), Nasik. -
Medisoft Hospital Management System (Sponsored by Himachal Futuristic Communication Ltd., Gurgaon)
Skills
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Programming Languages : C, C++, Perl, MATLAB, Python
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Assembly Languages : Intel (8085, 8086, 8051, 8031), PIC Microcontroller, Motorola (MC68000)
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Hardware Description Languages (HDLs) : VHDL, Verilog
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Hardware Verification Languages (HVLs) : Open VERA, System-Verilog
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VLSI Synthesis Tools : Xilinx, Tanner, FPGA Adv
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VLSI Simulation Tools :Active HDL, Nc Verilog
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Other Simulation Tools : TSPICE, PSPICE
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Environments : Windows, GNU/LINUX, UNIX (Sun Solaris)