top of page

Paper Presented / Published

  • Presented the paper entitled "Analysis and Classification of Diabetic Retinopathy images using light weight models" in International Conference on Additive Manufacturing Technologies (Aerospace, Automobile, AI&ml, Biomedical, Computer Science, Electrical, Electronics, Mechanical, Petrochemical and Construction - 3DP) 17-18 October, 2024.

  • Published Paper entitled "Deep learning based binary classification of diabetic retinopathy images using transfer learning approach" in Journal of Diabetes & Metabolic Disorders Volume 23, pages 2289–2314, (2024)

  • Presented Paper in International Conference on Recent Trends  in Science, Technology and Management (ICRTSTM) 2024 from June 28-29 2024 at Bharati Vidyapeeth Pune on title " "Recent Development and Application in Deep Learning for Diabetic Retinopathy Image Classification" 

  • Presented 2 Papers in International Conference on Technological Innovative Transformation to Industry 5.0 (ICTII 2024) held at DCE, Gurgaon on March 23-24, 2024.

  • Seema, "Unifed intercept probability analysis of multi‐user multi‐relay aided decode‐and‐forward wireless systems" is published in Int. j. inf. tecnol. https://doi.org/10.1007/s41870-024-01763-8 (Scopus Paper(11/3/24)

  • Seema, S.S Chauhan, "Linearity performance analysis of double gate (DG) VTFET using HDB for RF applications" is published in Silicon, Vol. 13, pp. 1121-1125, 2021. (SCI Indexed).

  •  Seema, S.S Chauhan, "Performance investigation of electrode work-function engineered hetero-dielectric buried oxide vertical TFET", is published in IET Circuits, Devices & Systems, Vol. 13, no. 7, pp. 1027-1031, 2019. (SCI Indexed).

  •  Seema, S.S Chauhan, "Investigation of RF and Linearity Performance of electrode work-function engineered HDB Vertical TFET", is published in IET Micro & Nano Letters, Vol. 14, no. 1, pp. 17-21, 2019. (SCI Indexed).

  •  Seema, S.S Chauhan, "A new design approach to improve DC, analog/RF and linearity metrics of Vertical TFET for RFIC design", is published in Superlattices and Microstructures, Vol. 122, pp. 286-295, 2018. (SCI Indexed).

  •  Seema, S.S Chauhan, "Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation" is published in Superlattices and Microstructures, Vol. 117, pp. 1-8, 2018. (SCI Indexed).

  •  Seema, et al., "Study of Optimization Techniques of renewable energy resources to increase the efficiency of smart grid for power sector in India" is published in International Journal for Scientific Research and Development, Vol. 4, no. 9, pp. 677-680, ISSN 2321-0613, 2016. (Impact Factor- 2.39) (Peer-reviewed, Google Scholar Indexed).

  •  Seema, et al., "Solar Car- A step to save non-renewable sources of energy" is presented in National Conference on Development & Advancement in Smart Grid for Solar Renewable Energy, Technically co-sponsored by SERB, DST, New Delhi, Gurgaon, 2016.

  •  Seema, et al., "LiFi using Solar Energy" is presented in National Conference on Development & Advancement in Smart Grid for Solar Renewable Energy, Technically co-sponsored by SERB, DST, New Delhi, Gurgaon, 2016.

  •  Seema, “Radiation Hard Charge Pump and Loop Filter” is presented in National Conference on Technological Developments in Electronics Engineering - Macro to Nano World, Technically co-sponsored by SERB, DST, MHRD, New delhi, Gurgaon, 2015.

  •  Seema, Nishanth Mehnathan, “Characterization and simulation of Invar-36 electrodeposition for MEMS” is presented in National Conference on Technological Developments in Electronics Engineering - Macro to Nano World, Technically co-sponsored by SERB, DST, MHRD, New delhi, Gurgaon, 2015.

  •  Seema Narwal, Rohit Singh Joon, “Design and Analysis of Pass Transistor logic based Implicit Pulse-triggered Flip-flop” is presented in International Conference on Signal Propagation and Computer Technology, Technically Co-sponsored by IEEE Delhi Section, Ajmer, 2014.

  •  Seema Narwal, Vandana chahar, “FPGA based hardware implementation of variant DPCM image compression technique (Multiple LUT-DPCM)” is Published in International Journal of Applied Information Systems, Foundation of Computer Science FCS, New York, USA, ISBN- 978-93-65823-70-9, ISSN 2249-0868, Vol-7, No.-1, pp.16-19, 2014 (This article is available in Harvard Network)(doi-10.5120).

  •  Seema, Raj kamal, “Design and Simulation of full-adder using a minimal transistor CMOS XOR-XNOR cell for low-power VLSI Design” Proceedings of National Conference on Recent Advances in Science, Engineering & Management , Bahadurgarh, 2014.

  •  Seema Narwal, Shikha Singh “Comparison of Single Bit 14 T and 8T Full Adder for Low- Power VLSI Design” Proceedings of International Conference on Emerging Trends in Engineering & Technology, Technically Co-sponsored by ACEEE, IDES, USA, Kurukshetra, 2013.

  •  Seema, Shikha “Comparative Performance Analysis of XOR/XNOR Topologies for Low- Power VLSI Design” is Published in International Journal of Engineering Research and Technology, ISSN 2249-3131, Vol-6, No.-10, pp.25-31, 2013 (Impact Factor- 1.76).

bottom of page