PROJECTS SUMMARY
Verification of I2C SoC Subsystem
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Description: On SOC I2C functions as master only, in two modes: normal and fast, allows clock stretching. Command and data FIFOs enable process of transmit, receive using standard external signals Serial clock (SCL) and Serial Data (SDA). Operation initiates with a start bit, addr, read/write operation, ack, data and terminates at stop bit. I2C interfaces with AMBA APB on SoC.
Role: Extracted features from specification to create test plan.
Wrote C test cases for I2C based upon extracted features.
HVL : TB Methodology
EDA Tool : System verilog,
C :Verilog :NC-SIM
Verification of Memory DMA SOC Subsystem
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Description: DMA is used to transfer data between internal memory to internal memory , internal to external memory or I/O Devices to memories. I worked on 32 bit data bus,8 channel DMA. Independent read/write arbitration feature is available. Separate FIFO’s are there to store write and read data.
Role: Understanding the Verification environment and the SoC Testbench Architecture.ï€ ï‚· Developed a Test plan .ï€ ï‚· Wrote C_test cases for DMA based upon extracted features.ï€
HVL : System verilog,C
TB Methodology : :Verilog
EDA Tool :NC-SIM
Verification of ADC SoC Subsystem:
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Description: This project involves the SoC-level verification of an Analog-to-Digital Converter (ADC). The SoC integrates a 12-channel ADC module for analog-to-digital signal conversion.
Role: Extracted features from specification to create test plan.ï€ ï‚· Wrote C test cases for ADC based upon extracted features.ï€ ï‚· Created context for GPADC.
HVL : System verilog,C
TB Methodology : :Verilog
EDA Tool :NC-SIM
CRR ( Common Register Repository):
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Description: Responsible for regenerating and updating the register header (base addresses, offsets, and mask values) in the SoC environment and releasing the corresponding VIP with updated patterns.
Role: CRR Header and VIP generation.
HVL : System verilog,C
TB Methodology : :Verilog
EDA Tool :NC-SIM
GLS ( Gate Level Simulation):
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Description: Performed gate-level regression on PD-provided netlists with SDF annotation across Best, Worst, and Typical timing corners.
Role: Setup the GLS environment.
Run regression for zero delay.
Handled regression for multiple blocks.
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HVL : System verilog, C
TB Methodology : :Verilog
EDA Tool :NC-SIM
CDC( Clock Domain Crossing):
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Description: Verified synchronization across clock domains using two-flip-flop synchronizers and ensured data stability for one and a half clock cycles.
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Role: Handled Central regression After enabling arg used for CDC and analyzed the failures.
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HVL : System verilog, C
TB Methodology : :Verilog
EDA Tool :NC-SIM
Verification of AMBA-AHB Lite protocol
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Description: AMBA-AHB Lite protocol is high performance system backbone bus, able to sustain the external memory bandwidth on which the CPU, on-chip memory and other DMA device reside. It is a multi-master multi-slave protocol having pipelined operation.
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Role: Studied the AMBA-AHB Lite protocol.
Created UVM based verification environment.
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HVL : System verilog
TB Methodology : :UVM
EDA Tool :NC-SIM
Verification of AMBA-AXI_3 protocol
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Description: We are using AMBA_AXI_3 protocol in our SoC Verification project with ARC770DD processor to drive the transactions. The AMBA_AXI_3 protocol is targeted at high-performance, high- frequency system and includes a number of features that make it suitable for a high-speed communication. AXI has five independent unidirection channel.
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Role: Studied the AMBA_AXI_3 protocol specification. ï‚· Developed the Verification Plan. ï‚· Created UVM based verification environment.
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HVL : System verilog
EDA Tool : Cadence NcSim, Simvision
Verification of SPI protocol
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Description: A full duplex serial peripheral interface consists of 4-wire signals interfacing SPI slave, using Chip select, serial clock, serial data input and serial data output.
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Role: Developed the Verification Plan. ï‚· Created UVM based verification environment.
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HVL : System verilog
EDA Tool : Cadence NcSim, Simvision
Verification of I2C protocol
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Description: We are using I2C in our SOC Project for onboard communication. In our project, we are having two 16*8 bit FIFOs. One for transmitting and other for receiving.
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Role: Developed the Verification Plan. ï‚· Created UVM based verification environment.
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HVL : System verilog
EDA Tool : Cadence NcSim, Simvision